An Application Specific Integrated Circuit (ASIC) is one example of a cell-based circuit. An ASIC includes at least one logic block customized for a particular use. A logic block is an arrangement of “cells” placed in a routing grid of vertical and horizontal “tracks.” Tracks are conductive structures, such as metallic structures, that provide routing over each of the cells. Two tracks, typically horizontal tracks, are used to provide power (VDD) and ground (VSS) to each of the cells. One track is usually reserved for power and thus is often called the VDD track; another track is usually reserved for ground and thus is often called the VSS track. The VDD track and the VSS track are frequently referred to jointly as the “power rails.”
The cells in a logic block are arranged in rows defined by the horizontal tracks. The height of each row, referred to as “track height,” is based on the number of horizontal tracks encompassing the cells on the row. Thus, a row having a track height of ten, i.e., a ten-track row, consists of ten horizontal tracks.
When designing and fabricating ASICs, cells are typically standard cells selected from cell libraries and placed in the logic blocks to expedite the process. The standard cells are predefined structures that represent design components used in a circuit. Each standard cell includes a group of transistors and interconnects that provide predefined functions such as logical or storage functions. Cell libraries include numerous standard cells that can be selected and combined to form a particular circuit design.
Usually, cells of a particular standard cell library are selected and laid out relative to the routing grid, which defines the horizontal and vertical tracks, to form a logic block. The “height” of a cell is determined by the number of horizontal tracks extending between the uppermost and lowermost points of the cell. The “width” of a cell is determined by the vertical tracks extending between the leftmost and rightmost points of the cell. In a conventional cell library, the standard cells usually have the same cell height. For example, a cell library would include multiple cells having a cell height of ten tracks, i.e., ten-track cells.
Tools are available to assist in using the cell libraries to automate the synthesis, placement and routing of the cells to form the logic blocks. Synthesis tools automatically select standard cells from a cell library to form an interconnected list (often called a “netlist”) of cells to represent the required functionality of an ASIC or a portion of an ASIC. Following synthesis, a placement tool initiates the physical implementation of the logic blocks by automatically assigning locations of the standard cells on the netlist to a two-dimensional floor plan that forms the logic block. A routing tool then adds the power rails and signal connect lines for the standard cells placed in the logic block. A lay out tool is then used to construct a representation in three-dimensions of the logic block. The representation includes, for example, n-doped regions (“n-well”) and p-doped regions (“p-well”) of semiconductor substrate designated for the various standard cells.
As a result of modern tool capability and library construction techniques, logic blocks made up of standard cells allow complex circuits, such as ASICs, to be designed efficiently. Nevertheless, improvements in the design and fabrication of logic blocks would prove beneficial in the art.